A novel elevated source/drain PMOSFET formed by Ge-B/Si intermixing

Author

Ranade, Pushkar ; Takeuchi, Hideki ; Subramanian, Vivek ; King, Tsu-Jae

Author_Institution

Dept. of Mater. Sci. & Eng., California Univ., Berkeley, CA, USA

Volume

23

Issue

4

fYear

2002

fDate

4/1/2002 12:00:00 AM

Firstpage

218

Lastpage

220

Abstract

Driven by strain relaxation, the rapid thermal annealing (RTA) of B-doped Ge on an Si substrate forms graded Si/sub 1-x/Ge/sub x/ layers with B confined inside. Based on this observation of Ge-B/Si intermixing, a novel elevated source/drain (S/D) PMOSFET fabrication process is proposed. The new process consists of three simple steps: (a) selective Ge deposition in S/D regions by conventional LPCVD, (b) B implantation, and (c) RTA for Ge-B/Si intermixing to form S/D extensions to the channel. Fabricated PMOSFETs with sub-100 nm gate lengths display excellent short channel performance.

Keywords

MOSFET; boron; chemical interdiffusion; chemical vapour deposition; elemental semiconductors; germanium; ion implantation; rapid thermal annealing; semiconductor technology; silicon; 100 nm; B implantation; B-doped Ge; Ge-B/Si intermixing; Ge-Si:B; LPCVD; RTA; Si; Si substrate; elevated source/drain PMOSFET fabrication; graded Si/sub 1-x/Ge/sub x/ layers; rapid thermal annealing; selective Ge deposition; sub-100 nm gate; CMOS technology; Capacitive sensors; Contact resistance; Dielectric substrates; Displays; Fabrication; MOSFET circuits; Rapid thermal annealing; Rapid thermal processing;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.992844

Filename

992844