DocumentCode :
1266517
Title :
Gate length dependent polysilicon depletion effects
Author :
Choi, Chang-Hoon ; Chidambaram, P.R. ; Khamankar, Rajesh ; Machala, Charles F. ; Yu, Zhiping ; Dutton, Robert W.
Author_Institution :
Center for Integrated Syst., Stanford Univ., CA, USA
Volume :
23
Issue :
4
fYear :
2002
fDate :
4/1/2002 12:00:00 AM
Firstpage :
224
Lastpage :
226
Abstract :
Degradation of MOS gate capacitance in the inversion region becomes worse as the gate length is scaled down, according to a new experiment. Namely, the polysilicon depletion effect has gate length dependence. The origin of this gate length-dependent polydepletion effect has been modeled and verified by using device simulation. As a result, the gradient of dopant distribution resulting from ion implantation is shown to be an additional potential drop in the polygate. In addition, the enlarged depletion width at the gate sidewall can worsen the polydepletion effect for very-small MOSFETs.
Keywords :
MOSFET; capacitance; doping profiles; ion implantation; semiconductor device models; silicon; MOS gate capacitance degradation; device simulation; dopant distribution gradient; enlarged depletion width; gate length dependence; inversion region; ion implant; polydepletion effect model; polysilicon depletion effects; potential drop; very-small MOSFETs; CMOS process; Capacitance measurement; Implants; Impurities; Instruments; Ion implantation; MOS devices; MOSFETs; Semiconductor process modeling; Transconductance;
fLanguage :
English
Journal_Title :
Electron Device Letters, IEEE
Publisher :
ieee
ISSN :
0741-3106
Type :
jour
DOI :
10.1109/55.992846
Filename :
992846
Link To Document :
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