Title :
Three-dimensional CMOS integration
Author :
Neudeck, Gerold W.
Author_Institution :
Dept. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
The advantages of CMOS technology are examined, and problems of and approaches to 3-D integration are discussed. Particular attention is given to silicon-on-insulator (SOI) technology and the use of selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) of monocrystalline silicon. The fabrication of 3-D CMOS devices using these techniques is described.<>
Keywords :
CMOS integrated circuits; integrated circuit technology; semiconductor epitaxial layers; semiconductor growth; semiconductor-insulator boundaries; 3-D integration; CMOS technology; SOI; epitaxial lateral overgrowth; selective epitaxial growth; silicon-on-insulator; CMOS process; CMOS technology; Fabrication; MOS capacitors; MOS devices; Silicon on insulator technology; Switched capacitor circuits; Switches; Ultra large scale integration; Very large scale integration;
Journal_Title :
Circuits and Devices Magazine, IEEE
