Design of a 3780-point IFFT processor for TDS-OFDM

Author

Yang, Zhi-Xing ; Hu, Yu-Peng ; Pan, Chang-Yong ; Yang, Lin

Author_Institution

Dept. of Electron. Eng., Tsinghua Univ., Beijing, China

Volume

48

Issue

1

fYear

2002

fDate

3/1/2002 12:00:00 AM

Firstpage

57

Lastpage

61

Abstract

This correspondence presents a design of 3780-point IFFT processor for TDS-OFDM terrestrial DTV transmitter using FPGA. It demonstrates the algorithm design and error analysis of the processor, which can achieve a throughput of 7.56M complex IFFT operations per second. This design meets the signal-to-quantization noise ratio requirement of the TDS-OFDM system. It consists of two FPGA and one dual-port RAM. The data stream pipeline algorithm is implemented

Keywords

OFDM modulation; digital signal processing chips; digital television; fast Fourier transforms; field programmable gate arrays; high definition television; pipeline processing; synchronisation; television transmitters; time-domain synthesis; 3780-point IFFT processor; FPGA; TDS-OFDM; algorithm design; data stream pipeline algorithm; error analysis; inverse FFT; inverse fast Fourier transform; signal-to-quantization noise ratio; terrestrial DTV transmitter; throughput; time domain synchronous-OFDM; Algorithm design and analysis; Digital TV; Discrete Fourier transforms; Field programmable gate arrays; HDTV; Hardware; Pipeline processing; Signal processing algorithms; Streaming media; Transmitters;

fLanguage

English

Journal_Title

Broadcasting, IEEE Transactions on

Publisher

ieee

ISSN

0018-9316

Type

jour

DOI

10.1109/11.992857

Filename

992857