DocumentCode :
1266705
Title :
Constant charge erasing scheme for flash memories
Author :
Chimenton, Andrea ; Pellati, Paolo ; Olivo, Piero
Author_Institution :
Dipt. di Ingegneria, Ferrara Univ., Italy
Volume :
49
Issue :
4
fYear :
2002
fDate :
4/1/2002 12:00:00 AM
Firstpage :
613
Lastpage :
618
Abstract :
This paper presents a new erasing scheme for flash memories based on a sequence of bulk to gate-box pulses with increasing voltage amplitude. It is experimentally and analytically demonstrated that the erasing dynamics always reaches an equilibrium condition where each pulse induces a constant and controllable injected charge and, therefore, constant threshold shifts. The analytical study allows us to express both the final threshold voltage and the oxide electric field as a function of technological, physical, and electrical parameters. Electrical parameters can be conveniently adapted to control both the threshold voltage and the oxide fields, thus reducing oxide stresses. Advantages with respect to the standard box erasing scheme are theoretically and experimentally demonstrated
Keywords :
flash memories; integrated circuit reliability; integrated memory circuits; IC reliability; bulk to gate-box pulses; constant charge erasing scheme; constant threshold shifts; controllable injected charge; electrical parameters; equilibrium condition; erasing dynamics; flash memories; oxide electric field; oxide stresses reduction; pulse sequence; semiconductor memories; threshold voltage; voltage amplitude; Degradation; Flash memory; Integrated circuit reliability; Integrated circuit technology; Semiconductor device reliability; Semiconductor memory; Stress control; Threshold voltage; Tunneling; Voltage control;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/16.992870
Filename :
992870
Link To Document :
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