Study of SILC and interface trap generation due to high field stressing and its operating temperature dependence in 2.2 nm gate dielectrics

Author

Borse, D.G. ; Vaidya, S.J. ; Chandorkar, Arun N.

Author_Institution

Dept. of Electr. Eng., Indian Inst. of Technol., Mumbai, India

Volume

49

Issue

4

fYear

2002

fDate

4/1/2002 12:00:00 AM

Firstpage

699

Lastpage

701

Abstract

Reports study of metal-oxide-semiconductor (MOS) capacitors with 2.2 nm dry and N₂O grown gate dielectrics. Interface trap generation during constant voltage stressing at different operating temperatures (from 22°C to 90°C) has been investigated. The effect of nitrogen annealing (20 min) at 400°C on high temperature stress-induced interface traps was also studied

Keywords

MOS capacitors; MOS integrated circuits; VLSI; annealing; dielectric thin films; electron traps; integrated circuit measurement; integrated circuit reliability; leakage currents; 2.2 nm; 20 min; 22 to 90 degC; 400 degC; N₂O; SILC; Si-SiO₂; VLSI; constant voltage stressing; gate dielectrics; high field stressing; high temperature stress-induced traps; interface trap generation; metal-oxide-semiconductor capacitors; nitrogen annealing; operating temperatures; reliability issues; stress-induced leakage current; transconductance; Annealing; Circuits; Dielectrics; Electron traps; MOS capacitors; Nitrogen; Silicon; Temperature control; Temperature dependence; Very large scale integration;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.992883

Filename

992883