Title :
Vertical Silicon Nanowire Gate-All-Around Field Effect Transistor Based Nanoscale CMOS
Author :
Maheshwaram, Satish ; Manhas, S.K. ; Kaushal, Gaurav ; Anand, Bulusu ; Singh, Navab
Author_Institution :
Dept. of Electron. & Comput. Eng., Indian Inst. of Technol. Roorkee, Roorkee, India
Abstract :
In this letter, we investigate a novel vertical silicon nanowire-based (NW) complementary metal-oxide-semiconductor (CMOS) technology for logic applications. The performance and the behavior of two- and single-wire CMOS inverters are simulated and analyzed. We show that vertical NW based CMOS offers a reduction of up to 50% in layout area, along with delay reductions of 50% (two wire) and 30% (single wire) compared with fin-shaped field effect transistor (FinFET) technology. The results show that vertical NW CMOS technology has a very high potential for ultralow-power applications with a power saving of up to 75% and offers an excellent overall performance for deca-nanoscale CMOS.
Keywords :
CMOS logic circuits; MOSFET; field effect transistors; FinFET technology; complementary metal-oxide-semiconductor; fin-shaped field effect transistor; logic application; nanoscale CMOS technology; single-wire CMOS inverters; two-wire CMOS inverters; ultralow-power application; vertical silicon nanowire gate-all-around field effect transistor; CMOS integrated circuits; CMOS technology; Delay; FinFETs; Inverters; Logic gates; Semiconductor device modeling; Nanowire (NW) metal–oxide–semiconductor field-effect transistor (MOSFET); power; scaling; vertical complementary metal–oxide–semiconductor (CMOS);
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2011.2157076
