A selectively deposited poly-gate ITLDD process with self-aligned LDD/channel implantation

Author

Pfiester, James R. ; Baker, Frank K. ; Sivan, Richard D. ; Crain, Neil ; Lin, Jung-Hui ; Liaw, Ming ; Seelbach, Chris ; Gunderson, Craig ; Denning, Dean

Author_Institution

Motorola Inc., Austin, TX, USA

Volume

11

Issue

6

fYear

1990

fDate

6/1/1990 12:00:00 AM

Firstpage

253

Lastpage

255

Abstract

An inverse-T lightly doped drain (ITLDD) CMOS process which features improved hot-carrier effects and self-aligned source/drain and channel implantation profiles is presented. Compensation effects by the heavy channel doping on the light N/sup -//P/sup -/ profile are minimized in this ITLDD structure, because the implants are self-aligned to the polysilicon-gate edge. In addition, because selective polysilicon deposition rather than an incomplete poly-gate etchback is used to define the ITLDD structure, a simpler, more manufacturable process is obtained due to improved control of the thin poly-gate shelf thickness.<>

Keywords

CMOS integrated circuits; doping profiles; hot carriers; integrated circuit technology; ion implantation; CMOS process; heavy channel doping; hot-carrier effects; inverse-T lightly doped drain; light N/sup -//P/sup -/ profile; poly-gate shelf thickness; selective polysilicon deposition; selectively deposited poly-gate ITLDD process; self-aligned LDD/channel implantation; CMOS process; Doping profiles; Etching; Fabrication; Gold; Hafnium; Hot carrier effects; Hot carriers; Implants; Temperature;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.55271

Filename

55271