Fine-Grain Voltage Tuned Cache Architecture for Yield Management Under Process Variations

Author

Kong, Joonho ; Pan, Yan ; Ozdemir, Serkan ; Mohan, Anitha ; Memik, Gokhan ; Chung, Sung Woo

Author_Institution

Div. of Comput. & Commun. Eng., Korea Univ., Seoul, South Korea

Volume

20

Issue

8

fYear

2012

Firstpage

1532

Lastpage

1536

Abstract

Process variations cause large fluctuations in performance and power consumption in the manufactured chips, which eventually results in yield losses. In this paper, to mitigate access time failures and excessive leakage in caches, we propose a novel selective wordline boosting mechanism combined with SRAM cell arrays voltage lowering. Based on our evaluation, the proposed approach recovers up to 83.1% of the yield losses.

Keywords

SRAM chips; cache storage; integrated circuit yield; memory architecture; power consumption; SRAM cell array; access time failure mitigation; cache leakage; fine-grain voltage tuned cache architecture; manufactured chip; power consumption; process variation; selective wordline boosting mechanism; voltage lowering; yield loss; yield management; Circuit faults; Computer architecture; Delay; Energy consumption; Microprocessors; Random access memory; Cache; process variation; selective wordline voltage boosting; supply voltage lowering; yield;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2011.2159634

Filename

5945008