A variable delay line PLL for CPU-coprocessor synchronization

Author

Johnson, Mark G. ; Hudson, Edwin L.

Author_Institution

MIPS Comput. Syst. Inc., Sunnyvale, CA, USA

Volume

23

Issue

5

fYear

1988

fDate

10/1/1988 12:00:00 AM

Firstpage

1218

Lastpage

1223

Abstract

A fully integrated phase-locked loop (PLL) is used to time-align the hi-Z/low-Z transitions of a CMOS CPU and its floating-point coprocessor (FPC), resulting in minimum timing difference (skew) between the two devices at their shared data bus, and decreasing the bus cycle time. The PLL circuit abandons the traditional voltage-controlled oscillator function, instead using a CMOS voltage-controlled delay line to improve noise immunity, ease loop stabilization, and permit dynamically adjustable clock periods. With the PLL enable, measured timing skew between the CPU and FPC is below 1 ns

Keywords

CMOS integrated circuits; delay lines; phase-locked loops; satellite computers; synchronisation; CMOS; CMOS voltage-controlled delay line; CPU-coprocessor synchronization; FPC; bus cycle time minimisation; dynamically adjustable clock periods; floating-point coprocessor; improve noise immunity; integrated phase-locked loop; loop stabilization; shared data bus; time alignment; timing skew minimisation; variable delay line PLL; CMOS process; Central Processing Unit; Clocks; Coprocessors; Delay lines; Flexible printed circuits; Manufacturing processes; Phase locked loops; Synchronization; Timing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.5947

Filename

5947