DocumentCode :
12676
Title :
Stability Analysis of Bang-Bang Phase-Locked Loops for Clock and Data Recovery Systems
Author :
Jae-Yong Ihm
Author_Institution :
Syst. LSI Bus., Samsung Electron. Co., Ltd., Yongin, South Korea
Volume :
60
Issue :
1
fYear :
2013
fDate :
Jan. 2013
Firstpage :
1
Lastpage :
5
Abstract :
Bang-bang phase detector-based phase-locked loops (PLLs) with first- and second-order analog loop filters (LFs) are considered. Discrete-time (DT) models are presented for the bang-bang PLLs (BPLLs) in the presence of loop delays. The DT models show that the delay introduces an additional pole at in the DT open-loop transfer function. The pole is of multiple order proportional to the delay, indicating that the system is prone to be unstable. Stability analysis of the BPLLs is conducted to derive stability conditions, taking advantage of the radius of curvature technique to facilitate numerical calculations involved. It is shown that the stability conditions depend on the LF parameters, the loop delay, and the update time of the BPLLs.
Keywords :
clocks; phase locked loops; stability; synchronisation; analog loop filters; bang bang PLL; bang bang phase detector; bang bang phase locked loops; clock recovery system; curvature technique; data recovery system; discrete time model; loop delays; numerical calculation; open loop transfer function; stability analysis; stability conditions; Circuit stability; Clocks; Delay; Mathematical model; Phase locked loops; Stability analysis; Transfer functions; Bang-bang phase detector (PD) (BPD); clock-and-data recovery; phase-locked loop (PLL); radius of curvature; root locus; stability condition;
fLanguage :
English
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-7747
Type :
jour
DOI :
10.1109/TCSII.2012.2234913
Filename :
6412783
Link To Document :
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