Architectural Characterization and Code Compression in Embedded Processors

Author

Dias, W.R.A. ; Moreno, E.D. ; Barreto, R. Da S

Author_Institution

Univ. Fed. do Amazonas (UFAM), Manaus, Brazil

Volume

10

Issue

4

fYear

2012

fDate

6/1/2012 12:00:00 AM

Firstpage

1865

Lastpage

1873

Abstract

This paper presents an architectural analysis of three processors RISC of 32 bits such as: ARM, PowerPC and XScale, used very in embedded systems. Simulation with the SimpleScalar tool was carried through on programs of the MiBench (a benchmark for embedded systems). The experiments show the number of instructions executed, the simulation time (in seconds and processor cycles), issuance of cycles per instruction (CPI) and the percentage of losses in the cache (miss rate) of data and instructions, emphasizing the impact of compression coding of the instructions of the benchmark using the Huffman algorithm, which was around 34% (compression software) for embedded applications, and also compared with an IP core for code compression described in VHDL and prototyped on an FPGA, that showed similar taxes of compression to the Huffman in software, being then of the 32% order (compression in the hardware).

Keywords

Huffman codes; cache storage; field programmable gate arrays; hardware description languages; logic circuits; microprocessor chips; reduced instruction set computing; ARM; FPGA; Huffman algorithm; IP core; MiBench; PowerPC; SimpleScalar tool; VHDL; XScale; architectural characterization; cache; code compression; compression software; embedded processors; processor cycles; processors RISC; Benchmark testing; Embedded systems; GSM; Reduced instruction set computing; Transform coding; Architectural Characterization; Compression Instruction; Embedded Processors; Embedded Systems and Simulation Architecture;

fLanguage

English

Journal_Title

Latin America Transactions, IEEE (Revista IEEE America Latina)

Publisher

ieee

ISSN

1548-0992

Type

jour

DOI

10.1109/TLA.2012.6272467

Filename

6272467