A Cascade-Parallel Based Noise De-Embedding Technique for RF Modeling of CMOS Device

In this letter, a unique cascade-parallel based noise de-embedding technique is presented for on-wafer device characterization and modeling. It utilizes two fully shielded THRU line structures and one OPEN structure that enable simultaneously de-embedding of series contact resistance, forward coupling and distributed parasitics of interconnect. Thus, it is more suitable for RF/millimeter wave noise characterization of lossy CMOS devices as compared to conventional lumped and cascade based de-embedding techniques. The proposed noise de-embedding technique is verified on both zero length THRU and OPEN devices. It demonstrates a better high frequency de-embedding performance than existing cascade based techniques by showing 1 dB improvement in predicted NFmin of 0.13 μm CMOS devices at 60 GHz. This is consistent with the further validation result on the de-embedded gain performance of the transistor.