Testability and test compaction for decision diagram circuits

Author

Bystrov, A. ; Almaini, A.E.A.

Author_Institution

Sch. of Eng., Napier Univ. of Edinburgh, UK

Volume

146

Issue

4

fYear

1999

fDate

8/1/1999 12:00:00 AM

Firstpage

153

Lastpage

158

Abstract

Novel node realisations are used to represent reduced ordered binary, functional and Kronecker decision diagrams as irredundant combinational circuits. These types of decision diagrams are compact and able to represent very large switching functions. The resulting circuits are completely testable in the single and multiple stuck-at fault models. Theorems on diagnostic properties of these circuits are formulated. The high complexity of functions represented by decision diagram circuits calls for efficient test pattern generation and test set compaction tools. Such tools were implemented using a genetic algorithm which maximises the number of potential faults covered by every test pattern. Experimental results for decision diagrams with up to 1763 inputs and 5329 nodes are presented. The efficiency of the genetic algorithm in this application is estimated

Keywords

VLSI; automatic test pattern generation; combinational circuits; decision diagrams; fault diagnosis; genetic algorithms; logic testing; switching functions; Kronecker decision diagrams; binary decision diagrams; decision diagram circuits; diagnostic properties; functional decision diagrams; genetic algorithm; irredundant combinational circuits; node realisations; stuck-at fault models; switching functions; test compaction; test pattern generation;

fLanguage

English

Journal_Title

Circuits, Devices and Systems, IEE Proceedings -

Publisher

iet

ISSN

1350-2409

Type

jour

DOI

10.1049/ip-cds:19990536

Filename

803788