Low power parallel spread-spectrum correlator

Direct sequence spread spectrum (DSSS) transmissions require a despreading stage within the standard receiver block to recover the spread spectrum signal. For long spread spectrum codes, the correlation block can be a large portion of the receiver size, hence a considerable portion of the power consumption. The authors look at two power reduction alternatives for a parallel spread spectrum correlator, by analysing the algorithm and designing a baseline correlator and by investigating how to streamline the arithmetic operations in one case, and optimising the sample storage in the other. The two correlator designs are compared with a mix of analytical techniques and simulation data to determine the optimal correlator alternative for the DSSS application. The final analysis shows that the register file based correlator can reduce the power by over 30% for bus widths greater than 6 by using a structure which maintains the multi-bit data samples in a static area and by rotating the single bit coefficients around the data with a circular shift register