Title :
A symmetric CMOS NOR gate for high-speed applications
Author :
Johnson, Mark G.
Author_Institution :
MIPS Comput. Syst. Inc., Sunnyvale, CA, USA
fDate :
10/1/1988 12:00:00 AM
Abstract :
A novel CMOS n-input NOR gate is proposed, having n parallel NMOS pull-downs to Vss and n parallel PMOS pull-ups to Vcc. The structure, which consumes DC power, is approximately twice as fast as a conventional full-CMOS NOR gate, and is slightly faster than a CMOS inverter. For gates with small fan-in (n⩽3), the proposed circuit is also faster than the grounded-PMOS NOR gate when operated at equal DC power levels
Keywords :
CMOS integrated circuits; integrated circuit technology; integrated logic circuits; logic gates; consumes DC power; fast; high-speed applications; parallel NMOS pull-downs; parallel PMOS pull-ups; symmetric CMOS NOR gate; Capacitance; Circuit noise; Intrusion detection; Inverters; MOS devices; MOSFETs; Microprocessors; Propagation delay; Switching circuits; Variable structure systems;
Journal_Title :
Solid-State Circuits, IEEE Journal of
