• DocumentCode
    1269180
  • Title

    A symmetric CMOS NOR gate for high-speed applications

  • Author

    Johnson, Mark G.

  • Author_Institution
    MIPS Comput. Syst. Inc., Sunnyvale, CA, USA
  • Volume
    23
  • Issue
    5
  • fYear
    1988
  • fDate
    10/1/1988 12:00:00 AM
  • Firstpage
    1233
  • Lastpage
    1236
  • Abstract
    A novel CMOS n-input NOR gate is proposed, having n parallel NMOS pull-downs to Vss and n parallel PMOS pull-ups to Vcc. The structure, which consumes DC power, is approximately twice as fast as a conventional full-CMOS NOR gate, and is slightly faster than a CMOS inverter. For gates with small fan-in (n⩽3), the proposed circuit is also faster than the grounded-PMOS NOR gate when operated at equal DC power levels
  • Keywords
    CMOS integrated circuits; integrated circuit technology; integrated logic circuits; logic gates; consumes DC power; fast; high-speed applications; parallel NMOS pull-downs; parallel PMOS pull-ups; symmetric CMOS NOR gate; Capacitance; Circuit noise; Intrusion detection; Inverters; MOS devices; MOSFETs; Microprocessors; Propagation delay; Switching circuits; Variable structure systems;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/4.5949
  • Filename
    5949
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1269180