Title :
Long and short covering edges in combination logic circuits
Author :
Li, Wing-Ning ; Reddy, Sudhakar M. ; Sahni, Sartaj
Author_Institution :
Dept. of Comput. Sci., Arkansas Univ., Fayetteville, AR, USA
fDate :
12/1/1990 12:00:00 AM
Abstract :
The polynomial time algorithm obtained earlier by the authors is extended to find a minimal cardinality path set that long covers each lead or gate input of a digital logic circuit. It is shown how to find, in polynomial time, a minimal cardinality set MinMaxSP for a given combinational logic circuit. Combinational circuit verification is used to verify the sequential circuit delays
Keywords :
combinatorial circuits; logic CAD; MinMaxSP; combination logic circuits; long covering edges; minimal cardinality path set; polynomial time algorithm; short covering edges; Circuit testing; Combinational circuits; Delay; Electrical fault detection; Flip-flops; Logic circuits; Pipelines; Sequential circuits; Signal design; Timing;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
