Title :
A neural network design for circuit partitioning
Author :
Yih, J.-S. ; Mazumder, Pinaki
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
fDate :
12/1/1990 12:00:00 AM
Abstract :
A neural network model is proposed for circuit bipartitioning. The massive parallelism of neural nets has been successfully exploited to balance the partitions of circuit and to reduce the external wiring between the partitions. The experimental results obtained by neural nets are found to be comparable with those achieved by the C.M. Fiduccia and R.M. Mattheyses (1982) algorithm. The proposed approach can be implemented in hardware to accelerate time-consuming partitioning procedures
Keywords :
circuit layout CAD; neural nets; CAD; circuit bipartitioning; circuit partitioning; layout design; neural network design; Acceleration; Artificial neural networks; Hardware; Integrated circuit interconnections; Minimization; Neural networks; Parallel processing; Partitioning algorithms; Wires; Wiring;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
