DocumentCode
1269320
Title
A neural network design for circuit partitioning
Author
Yih, J.-S. ; Mazumder, Pinaki
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
Volume
9
Issue
12
fYear
1990
fDate
12/1/1990 12:00:00 AM
Firstpage
1265
Lastpage
1271
Abstract
A neural network model is proposed for circuit bipartitioning. The massive parallelism of neural nets has been successfully exploited to balance the partitions of circuit and to reduce the external wiring between the partitions. The experimental results obtained by neural nets are found to be comparable with those achieved by the C.M. Fiduccia and R.M. Mattheyses (1982) algorithm. The proposed approach can be implemented in hardware to accelerate time-consuming partitioning procedures
Keywords
circuit layout CAD; neural nets; CAD; circuit bipartitioning; circuit partitioning; layout design; neural network design; Acceleration; Artificial neural networks; Hardware; Integrated circuit interconnections; Minimization; Neural networks; Parallel processing; Partitioning algorithms; Wires; Wiring;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.62771
Filename
62771
Link To Document