DocumentCode :
1269584
Title :
Leading-one prediction with concurrent position correction
Author :
Bruguera, Javier D. ; Lang, Tomás
Author_Institution :
Dept. of Electron. & Comput. Eng., Santiago de Compostela Univ., Spain
Volume :
48
Issue :
10
fYear :
1999
fDate :
10/1/1999 12:00:00 AM
Firstpage :
1083
Lastpage :
1097
Abstract :
This paper describes the design of a leading-one prediction (LOP) logic for floating-point addition with an exact determination of the shift amount for normalization of the adder result. Leading-one prediction is a technique to calculate the number of leading zeros of the result in parallel with the addition. However, the prediction might be in error by one bit and previous schemes to correct this error result in a delay increase. The design presented here incorporates a concurrent position correction logic, operating in parallel with the LOP, to detect the presence of that error and produce the correct shift amount. We describe the error detection as part of the overall LOP, perform estimates of its delay and complexity, and compare with previous schemes
Keywords :
adders; floating point arithmetic; adder result; complexity; concurrent position correction logic; delay; error detection; floating-point addition; leading zeros; leading-one prediction; Computer Society; Delay estimation; Detectors; Encoding; Error correction; Logic design; Process design; Proposals;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/12.805157
Filename :
805157
Link To Document :
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