Blanket SMT With In Situ N2 Plasma Treatment on the $\langle \hbox {100} \rangle$ Wafer for the Low-Cost Low-Power Technology App

PMOS degradation with the blanket-stress-memory-technique (SMT) nitride layer on the (100) wafer with ?100? orientation has been observed, and the degradation mechanism is examined. The boron-doping loss from both the PMOS gate and the source/drain region during the SMT process is the root cause. In situ N2 plasma treatment before the SMT layer deposition has been implemented for the first time to recover PMOS performance on the ?100? wafer by reducing the boron-doping loss from the gate and the source/drain region. Reliability like PMOS NBTI has been examined, and no degradation is observed.