Title :
A hidden surface and shading processor (HSSP) with a systolic architecture
Author :
Nishizawa, Teiji ; Ohgi, Takeru ; Kamiyama, Hiroshi ; Nagatomi, Kazuyasu ; Maenobu, Kiyoshi
Author_Institution :
Matsushita Electr. Ind. Co., Ltd., Osaka, Japan
fDate :
10/1/1988 12:00:00 AM
Abstract :
The HSSP processor for 3-D graphics applications is described. The HSSP chip has a regular structure owing to a skewed systolic array architecture. This novel VLSI-oriented architecture was applied to real-time 3-D graphics image generation, which requires very high processing throughput. The HSSP eliminates hidden portions of surfaces from a viewer, and gives a constant intensity or a smooth shaded intensity to each surface. It uses a scan-line Z-buffer algorithm, and outputs the resulting image in the scan line, pixel by pixel in a serial manner. The chip is fabricated in 1.2-μm twin-tub CMOS technology. It contains 330 K transistors on a 11.06×11.05-mm die, and operates with a 20-MHz single-phase clock
Keywords :
CMOS integrated circuits; VLSI; cellular arrays; computer graphic equipment; microprocessor chips; multiprocessing systems; special purpose computers; 1.2 micron; 11.06 mm; 20 MHz; 3-D graphics applications; HSSP chip; HSSP processor; VLSI-oriented architecture; constant intensity; eliminates hidden portions of surfaces; hidden surface and shading processor; high processing throughput; pixel by pixel; real-time 3-D graphics image generation; regular structure; scan-line Z-buffer algorithm; serial manner; single-phase clock; skewed systolic array architecture; smooth shaded intensity; systolic architecture; twin-tub CMOS technology; CMOS process; CMOS technology; Clocks; Computer graphics; Image generation; Microcomputers; Power system reliability; Smart pixels; Solid state circuits; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
