Formal verification of memory circuits by switch-level simulation

Author

Bryant, Randal E.

Author_Institution

Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA

Volume

10

Issue

1

fYear

1991

fDate

1/1/1991 12:00:00 AM

Firstpage

94

Lastpage

102

Abstract

An N-bit RAM can be verified by simulating just O(N log N) patterns. This approach to verification is fast, requires minimal attention on the part of the user to the circuit details, and can utilize more sophisticated circuit models than other approaches to formal verification. The technique has been applied to a CMOS static RAM design using the COSMOS switch-level simulator. By simulating many patterns in parallel, a massively parallel computer can verify a 4K RAM in under 6 min

Keywords

CMOS integrated circuits; automatic testing; digital simulation; integrated circuit testing; integrated memory circuits; logic testing; random-access storage; 4 KB; CMOS static RAM design; COSMOS switch-level simulator; IC testing; N-bit RAM; circuit models; massively parallel computer; memory circuits; switch-level simulation; three valued modelling; Circuit simulation; Circuit synthesis; Circuit testing; Computational modeling; Computer simulation; Formal verification; Logic circuits; Random access memory; Read-write memory; Switching circuits;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.62795

Filename

62795