Title :
Guest editorial - system-level interconnect prediction
Author :
Stroobandt, Dirk
Author_Institution :
Postdoctoral Researcher at Ghent University
fDate :
4/1/2002 12:00:00 AM
Keywords :
Clocks; Copper; Costs; Delay estimation; Design engineering; Design optimization; Integrated circuit interconnections; Very large scale integration; Wire;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2002.994996
