• DocumentCode
    1271180
  • Title

    Impact of unrealistic worst case modeling on the performance of VLSI circuits in deep submicron CMOS technologies

  • Author

    Nardi, Alessandra ; Neviani, Andrea ; Zanoni, Enrico ; Quarantelli, Michele ; Guardiani, Carlo

  • Author_Institution
    Dipt. di Elettronica e Inf., Padova Univ., Italy
  • Volume
    12
  • Issue
    4
  • fYear
    1999
  • fDate
    11/1/1999 12:00:00 AM
  • Firstpage
    396
  • Lastpage
    402
  • Abstract
    The impact of process fluctuations on the variability of deep submicron (DSM) very large scale integration (VLSI) circuit performances is investigated in this paper. In particular, we show that as process dimensions stale down in the subhalfmicron region, the relative weight of process variability tends to increase, thus wearing down a non negligible portion of the benefits that are expected from minimum feature size scaling. We still show that in order to better exploit the advance of process technology, it is essential to adopt a realistic approach to worst case modeling [assigned probability technique (APT)]. The application of the APT technique to different test circuits designed in 0.35, 0.25, and 0.18 μm CMOS technologies with a power supply ranging from 3.3 V down to 1 V will demonstrate how the manufacturability of DSM designs is going to be a vital factor for the successful implementation of high-performance or low-power systems in 0.18 μm and lesser technologies
  • Keywords
    CMOS integrated circuits; VLSI; integrated circuit design; integrated circuit modelling; low-power electronics; 0.18 micron; 0.25 micron; 0.35 micron; 1 to 3.3 V; VLSI circuit; assigned probability technique; deep submicron CMOS technology; low-power system; performance spread; process fluctuations; process variability; scaling; statistical design; worst case model; CMOS process; CMOS technology; Circuit testing; Computer aided software engineering; Fabrication; Fluctuations; Power supplies; Semiconductor device modeling; Stochastic processes; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Semiconductor Manufacturing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0894-6507
  • Type

    jour

  • DOI
    10.1109/66.806116
  • Filename
    806116