Latch-up DC triggering and holding characteristics of n-well, twin-tub and epitaxial CMOS technologies

Author

Pavan, P. ; Spiazzi, G. ; Zanoni, E. ; Muschitiello, M. ; Cecchetti, M.

Author_Institution

Dipartimento di Ellettronica e Inf., Padova Univ., Italy

Volume

138

Issue

5

fYear

1991

fDate

10/1/1991 12:00:00 AM

Firstpage

604

Lastpage

612

Abstract

The dependence of the latch-up susceptibility on layout parameters is studied on four stripe structures made using different CMOS processes: a standard n-well, a twin-tub and twin-tub epitaxial technology. The correlation between triggering currents, well and substrate resistances and parasitic transistor gains is studied by means of emitter current triggering measurements and two-dimensional simulations using HFIELDS. Triggering currents higher than 250 mA are obtained on epitaxial structures with n⁺ guard-rings. Anomalies in triggering and holding electrical characteristics are caused by the three-dimensional distribution of the latch-up current, which is observed by IR microscopy. These anomalies can affect results of conventional latch-up testing methods

Keywords

CMOS integrated circuits; digital simulation; electronic engineering computing; integrated circuit technology; optical microscopy; semiconductor device models; CMOS technologies; HFIELDS; IR microscopy; anomalies; emitter current triggering measurements; epitaxial structures; holding characteristics; latch up DC triggering; latch-up current; latch-up susceptibility; latch-up testing methods; layout parameters; n⁺ guard-rings; parasitic transistor gains; standard n-well; stripe structures; substrate resistances; three-dimensional distribution; triggering characteristics; triggering currents; twin-tub epitaxial technology; twin-tub technology; two-dimensional simulations;

fLanguage

English

Journal_Title

Circuits, Devices and Systems, IEE Proceedings G

Publisher

iet

ISSN

0956-3768

Type

jour

Filename

99509