• DocumentCode
    1272558
  • Title

    An efficient filter-based approach for combinational verification

  • Author

    Mukherjee, Rajarshi ; Jain, Jawahar ; Takayama, Koichiro ; Fujita, Masahiro ; Abraham, Jacob A. ; Fussell, Donald S.

  • Author_Institution
    Fujitsu Labs. of America, Sunnyvale, CA, USA
  • Volume
    18
  • Issue
    11
  • fYear
    1999
  • fDate
    11/1/1999 12:00:00 AM
  • Firstpage
    1542
  • Lastpage
    1557
  • Abstract
    Combinational verification is a co-NP complete problem. However, in reality, several techniques exist which perform reasonably well on many practical circuits. Also, it is often found that while one technique efficiently verifies a given circuit it fails badly on another circuit, whereas a certain other technique is efficient on the latter circuit but cannot handle the former circuit. Therefore, clearly, a robust verification methodology cannot depend on any single technique. Our goal in this research is to build a verification methodology whose performance is more immune to circuit variations. We have developed a methodology where several fundamentally different techniques can be combined to provide efficient heuristic solutions to combinational verification, and possibly other intractable problems as well. Such an integrated methodology is far more robust and efficient on a majority of combinational verification problems than any single existing technique. In this paper, we discuss the methodology in detail and present verification results using a fully automated prototype of the proposed methodology. Using this methodology, we can verify many circuits which could not be efficiently verified using any published techniques available to us, and even by some popular commercial combinational verification programs
  • Keywords
    binary decision diagrams; circuit optimisation; combinational circuits; computational complexity; formal verification; logic partitioning; logic testing; ATPG; BDDs; circuit variations; co-NP complete problem; combinational verification; filter-based approach; heuristic solutions; logic partitioning; robust verification methodology; Automatic test pattern generation; Boolean functions; Circuits; Data structures; Filters; Helium; Industrial relations; Jacobian matrices; Prototypes; Robustness;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.806801
  • Filename
    806801