DocumentCode
1272577
Title
FACT: a framework for applying throughput and power optimizing transformations to control-flow-intensive behavioral descriptions
Author
Lakshminarayana, Ganesh ; Jha, Niraj K.
Author_Institution
C&C Res. Labs., NEC Res. Inst., Princeton, NJ, USA
Volume
18
Issue
11
fYear
1999
fDate
11/1/1999 12:00:00 AM
Firstpage
1577
Lastpage
1594
Abstract
In this paper, we present an algorithm for the application of a general class of transformations to control-flow intensive behavioral descriptions. Our algorithm is based on the observation that incorporation of scheduling information can help guide the selection and application of candidate transformations, and significantly enhance the quality of the synthesized solution. The efficacy of the selected throughput and power optimizing transformations is enhanced by the ability of our algorithm to transcend basic blocks in the behavioral description. This ability is imparted to our algorithm by a general technique we have devised. Our system currently supports associativity, commutativity, distributility, constant propagation, code motion, and loop unrolling. It is integrated with a scheduler which performs implicit loop unrolling and functional pipelining, and has the ability to parallelize the execution of independent iterative constructs, whose bodies can share resources. Other transformations can easily be incorporated within the framework. We demonstrate the efficacy of our algorithm by applying it to several commonly available benchmarks. Upon synthesis, behaviors transformed by the application of our algorithm showed, on an average, a 2.5-fold improvement in throughput over an existing transformation algorithm, and a 57.6% improvement in power over designs produced without the benefit of our algorithm
Keywords
data flow graphs; high level synthesis; optimisation; scheduling; FACT; associativity; code motion; commutativity; constant propagation; control-flow-intensive behavioral descriptions; distributility; functional pipelining; independent iterative constructs; loop unrolling; parallelization; power optimizing transformations; scheduling information; throughput optimizing transformations; Application software; Arithmetic; Associate members; Control system synthesis; High level synthesis; Iterative algorithms; Laboratories; Pipeline processing; Signal processing; Throughput;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.806804
Filename
806804
Link To Document