Title :
On comparing functional fault coverage and defect coverage for memory testing
Author :
Kim, Von-Kyoung ; Chen, Tom
Author_Institution :
Sun Microelectron., Palo Alto, CA, USA
fDate :
11/1/1999 12:00:00 AM
Abstract :
The manufacturing of high-quality and reliable semiconductor memories is very important. Many memory testing algorithms have been proposed to improve the quality of semiconductor memories by screening out different memory functional faults. However, the relationships between memory function fault types and the types of defects which cause the functional faults are not well understood. Therefore, the effectiveness of memory testing algorithms based on the functional fault models cannot be realistically determined. This paper evaluates the effectiveness of the memory testing algorithms based on the defect coverage by comparing the defect coverage of known memory testing algorithms and the functional fault coverage of the same testing algorithms using the same defect statistics. The experimental results show that the differences among the defect coverage of the 11 memory testing algorithms other than checkerboard and sliding diagonal tests were not significant as previously believed using memory functional fault coverage as the coverage metric
Keywords :
CMOS memory circuits; SRAM chips; automatic test pattern generation; boundary scan testing; fault simulation; integrated circuit testing; CMOS process; SRAM; defect coverage; defect statistics; fault probability prediction model; functional fault coverage; inductive fault analysis; memory testing; test effectiveness; testing algorithms; Algorithm design and analysis; Circuit faults; Costs; Fault detection; Legged locomotion; Semiconductor device manufacture; Semiconductor device reliability; Semiconductor device testing; Semiconductor memory; Statistical analysis;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on