A high speed VLSI architecture of discrete wavelet transform for MPEG-4

Author

Chang, Si Jung ; Lee, Moon Ho ; Park, Ju Yong

Author_Institution

Dept. of Inf. & Commun. Eng., Chonbuk Nat. Univ., Chonju, South Korea

Volume

43

Issue

3

fYear

1997

fDate

8/1/1997 12:00:00 AM

Firstpage

623

Lastpage

627

Abstract

We present a high speed VLSI architecture of the discrete wavelet transform (DWT) for MPEG-4. We found similarities between the computation results of each octave. By using the similarities, in the proposed architecture, the input data are separated between even and odd, and the two data streams are inputted in parallel. This causes faster discrete wavelet transform operation than other architectures. In conventional architectures, the N-point DWT is computed in N cycles or 2N cycles. Whereas, in the proposed architecture the N-point DWT is computed in N/2 cycles with 100% hardware utilization. Therefore, the proposed architecture can be applied in the MPEG-4 standard, image transmission in wireless networks and digital signal processing which require high speed processing

Keywords

VLSI; code standards; digital signal processing chips; parallel architectures; telecommunication standards; transform coding; transforms; video coding; visual communication; wavelet transforms; DWT; MPEG-4 standard; digital signal processing; discrete wavelet transform; hardware utilization; high speed VLSI architecture; high speed processing; image transmission; input data; parallel architecture; wireless networks; Computer architecture; Discrete wavelet transforms; Filtering; Frequency; Hardware; Image coding; Low pass filters; MPEG 4 Standard; Signal processing algorithms; Very large scale integration;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.628685

Filename

628685