A variable length coding ASIC chip for HDTV video encoders

Author

Yang, Jin-young ; Lee, Youngsun ; Lee, Hankyu ; Kim, Jinwoong

Author_Institution

Electron. & Telecommun. Res. Inst., South Korea

Volume

43

Issue

3

fYear

1997

fDate

8/1/1997 12:00:00 AM

Firstpage

633

Lastpage

638

Abstract

This paper describes functions and architecture of a VLC ASIC chip specially designed for a parallel processing HDTV video encoder. It is designed to have several operating modes which is very flexible in that it can process in a master or slave sub-picture encoding module of an HDTV encoder, as well as in a stand-alone encoder for several video input formats according to MPEG-2 MP@ML. The VLC chip is fabricated using 0.8 μm CMOS gate array technology, and runs at 27 MHz clock rate

Keywords

CMOS digital integrated circuits; application specific integrated circuits; code standards; digital signal processing chips; high definition television; logic arrays; parallel architectures; variable length codes; video coding; 0.8 micron; 27 MHz; ASIC chip; CMOS gate array technology; HDTV video encoders; MPEG-2 MP@ML; VLC chip; clock rate; master subpicture encoding module; operating modes; parallel processing; slave subpicture encoding module; stand-alone encoder; variable length coding; video input formats; Application specific integrated circuits; CMOS technology; Clocks; Encoding; HDTV; Hardware; Master-slave; Parallel processing; Streaming media; TV;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.628687

Filename

628687