Title :
New architecture for an AES-EBU digital audio receiver
Author :
Angelici, Marco ; Bianchessi, Marco ; Feste, Sandro Dalle ; Serina, Nadia
Author_Institution :
SGS-Thomson Microelectron., Milan, Italy
fDate :
8/1/1997 12:00:00 AM
Abstract :
This paper describes the realization of a digital audio receiver in accordance with the AES3 and S/PDIF format. It illustrates its realization and the performance obtained in terms of output jitter measured on the test chip. This receiver is realized in 3-metal layer 0.5 μm CMOS technology, and with a 3.3 V power supply. This low power supply makes the interface compatible with the new generation of VLSI circuits, although it increases the analog design difficulties
Keywords :
CMOS digital integrated circuits; VLSI; digital audio broadcasting; radio receivers; telecommunication standards; 0.5 micron; 3.3 V; AES-EBU digital audio receiver; AES3 format; CMOS technology; S/PDIF format; VLSI circuits; audio data exchange; audio receiver architecture; interface; measured output jitter; performance; power supply; test chip; CMOS technology; Clocks; Decoding; Frequency; Jitter; Phase locked loops; Phase modulation; Power supplies; Protocols; Sampling methods;
Journal_Title :
Consumer Electronics, IEEE Transactions on
