• DocumentCode
    1273206
  • Title

    Adaptive Body Bias for Reducing the Impacts of NBTI and Process Variations on 6T SRAM Cells

  • Author

    Mostafa, Hassan ; Anis, Mohab ; Elmasry, Mohamed

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Waterloo, ON, Canada
  • Volume
    58
  • Issue
    12
  • fYear
    2011
  • Firstpage
    2859
  • Lastpage
    2871
  • Abstract
    Reliability and variability have become big design challenges facing submicrometer SRAM designers. A low area overhead adaptive body bias (ABB) circuit is proposed in this paper to compensate for NBTI aging and process variations to improve the SRAM reliability and yield. The proposed ABB circuit consists of a threshold voltage sensing circuit and an on-chip analog controller. Postlayout simulation results, referring to an industrial hardware-calibrated STMicroelectronics 65 nm CMOS technology transistor model, are presented. The transistor model contains process variations and NBTI aging model cards, which are declared by STMicroelectronics to be silicon verified. Cadence RelXpert, Virtuoso Spectre, and Virtuoso UltraSim tools are used to estimate the NBTI aging and process variations impacts on the SRAM array. These results show that the proposed ABB compensates effectively for NBTI aging and process variations. For example, the proposed ABB reduces the read failure probability from 0.32% to 0.05% and the SNM degradation from 10.9% to 2.6% at 10 years aging time. In addition, the proposed ABB enhances the soft errors immunity of the SRAM cell by reducing the critical charge degradation from 12.7% to 3.4% at 10 years aging time.
  • Keywords
    CMOS integrated circuits; SRAM chips; semiconductor device reliability; CMOS technology transistor model; Cadence RelXpert; NBTI aging model card; SRAM array; SRAM cells; SRAM reliability; Virtuoso Spectre; Virtuoso UltraSim tools; adaptive body bias circuit; critical charge degradation; industrial hardware-calibrated STMicroelectronics; on-chip analog controller; process variation; soft errors immunity; submicrometer SRAM designer; threshold voltage sensing circuit; variability; CMOS integrated circuits; MOSFETs; Negative bias temperature instability; SRAM chips; Threshold voltage; Adaptive body bias; SRAM cells; deep submicrometer; negative bias temperature instability; process variations; soft errors;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems I: Regular Papers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1549-8328
  • Type

    jour

  • DOI
    10.1109/TCSI.2011.2158708
  • Filename
    5954143