DocumentCode
1273227
Title
A New Programming Scheme for the Improvement of Program Disturb Characteristics in Scaled nand Flash Memory
Author
Shirota, Riichiro ; Huang, Chen-Hao ; Nagai, Shinji ; Sakamoto, Yoshinori ; Li, Fu-Hai ; Mitiukhina, Nina ; Arakawa, Hideki
Author_Institution
Dept. of Electr. & Comput. Eng., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
Volume
59
Issue
10
fYear
2012
Firstpage
2767
Lastpage
2773
Abstract
This paper investigates the new programming scheme to reduce the program disturb in the NAND Flash memory. Program disturb characteristics are determined by the unwilling electron injections in the floating gate of the unselected cells during programming. Thus, the key point to improve the program disturb characteristics is how to suppress the electron injection in the unselected cells. This requirement can be implemented by reducing the number of electrons in the unselected NAND strings prior to programming. By applying negative bias to all the word lines in the selected block, excess electrons can be removed from the channel and source/drain regions into the bit line or the source line using drift and diffusion mechanisms, and also electrons in the surface states can be recombined with accumulated holes before programming. After the pretreatment of electron reduction in the NAND string, a normal NAND program sequence follows. The advantage of the pretreatment before programming has been verified by measuring the 8-Gb NAND Flash memory with a 50-nm technology node. Significant reduction of the threshold voltage shift was observed even after the severe program disturb stress, which corresponds to around 30 times of the programming of the 2 bit/cell operation.
Keywords
NAND circuits; flash memories; logic gates; NAND string; electron injection suppression; electron reduction pretreatment; floating gate; normal NAND program sequence; program disturb characteristics; programming scheme; scaled NAND flash memory; size 50 nm; source-drain regions; unselected NAND strings; unwilling electron injections; Boosting; Charge carrier processes; Electric potential; Flash memory; IEEE Potentials; Programming; Stress; Flash memory; Fowler–Nordheim (FN) tunneling; junction leakage (J/L); nand cell; program disturb; select gate (SG); surface state;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2012.2208462
Filename
6287010
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