The design of hybrid carry-lookahead/carry-select adders

Author

Wang, Yuke ; Pai, C. ; Song, Xiaoyu

Author_Institution

Dept. of Comput. Sci., Texas Univ., Richardson, TX, USA

Volume

49

Issue

1

fYear

2002

fDate

1/1/2002 12:00:00 AM

Firstpage

16

Lastpage

24

Abstract

In this paper, we present a general architecture for designing hybrid carry-lookahead/carry-select adders. Several previous adders in the literature are all special cases of this general architecture. They differ in the way Boolean functions for the carries are implemented. Based on the general architecture, we propose a new implementation of high-speed 56-bit hybrid adder. The new adder directly implements group carry propagates and group carry generators without individual carry generator/propagate signals. Moreover, the group carry generator/propagate signals are complemented to gain speed. The new implementation can be in static CMOS or dynamic logic style. The critical path length of our new design is about 2/3 of the critical path lengths of previous adders; therefore, higher speed can be gained

Keywords

Boolean functions; CMOS logic circuits; VLSI; adders; carry logic; high-speed integrated circuits; logic design; 56 bit; Boolean functions; dynamic logic style; general architecture; group carry generators; group carry propagates; high-speed hybrid adder; hybrid carry-lookahead/carry-select adders; static CMOS logic style; Adders; Boolean functions; CMOS logic circuits; CMOS technology; Computer performance; Computer science; Digital arithmetic; Hybrid power systems; Signal generators; Very large scale integration;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.996053

Filename

996053