Dynamic-range enhancement of an optimized 1-bit A/D converter

A technique is demonstrated for extending the dynamic range of 1-bit analog-to-digital converters (ADCs) that sample at the maximum rate using a sinusoid reference r(t)=A_r cos(2πf_rt). The ADC has a detection limit B=πA_r δ/▵, where 2δ_s is the base-clock period, and ▵=sampling interval=1/2f_r⩾2δ. Optimal sampling is achieved at ▵=2δ, but with large quantization errors found in the sampled representation of the input signal s(t). Dithering with noise n_σ(t) of appropriate variance σ² is utilized to measure a subthreshold s(t) where |s(t)|<B for all t. Both uniform white noise (UWN) and Gaussian white noise (GWN) are utilized. With UWN dithering at σ=B, we could reduce the errors to levels that are produced by an equivalent q-bit amplitude-sampling (bipolar) ADC by observing the dithered signal s(t)+n_σ(t) over a time duration of T[(0.116/|V|)(2^q-1)]^0.995, where T is the sampling period, and ±V are the ADC supply voltages. With GWN dithering at σ=0.5 B, the duration required is T[(0.109/V)(2^q-1)] ^0.996