• DocumentCode
    1273840
  • Title

    FPGA based runtime configurable clause evaluator for SAT problems

  • Author

    Leong, P.H.W. ; Chung, C.K.

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Chinese Univ. of Hong Kong, Shatin, Hong Kong
  • Volume
    35
  • Issue
    19
  • fYear
    1999
  • fDate
    9/16/1999 12:00:00 AM
  • Firstpage
    1618
  • Lastpage
    1619
  • Abstract
    An FPGA based clause evaluator for Boolean satisfiability problems is presented in which a customised bitstream is directly generated from the problem specification, avoiding the need for resynthesis. A three orders of magnitude improvement in reconfiguration time was seen over the standard approach for a 50 variable, 80 clause problem
  • Keywords
    Boolean functions; constraint theory; field programmable gate arrays; logic CAD; Boolean satisfiability problems; FPGA based clause evaluator; SAT problems; customised bitstream; runtime configurable clause evaluator;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19991132
  • Filename
    807026
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1273840