Title :
A 3 V 6-bit 70 MSPS dual CMOS A/D converter for DBS (direct broadcasting for satellite)
Author :
Lee, Ho-Young ; Park, Jae-Jin ; Song, Min-Kyu ; Kim, Jae-Whui ; Kim, Kwong-Hyun
Author_Institution :
Semicond. Micro Bus., Samsung Electron. Co. Ltd., South Korea
fDate :
8/1/1997 12:00:00 AM
Abstract :
In a front-end receiver of DBS (direct broadcasting for satellite), the A/D converter, which converts I/Q signals of the QPSK demodulator into the digital domain, has an important role in determining the system performance. A 3 V dual A/D converter which has a 6-b resolution and a 70 MSPS conversion rate is proposed. It has a dual flash architecture in which comparators use an auto-zero offset cancellation technique with 0.65 μm double-poly and double-metal CMOS technology, the experimental prototype of the proposed A/D converter has ±0.7 LSB INL (integral non-linearity error) and ±0.9 LSB DNL (differential non-linearity error)
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; comparators (circuits); demodulators; digital television; direct broadcasting by satellite; quadrature amplitude modulation; television receivers; 0.65 micron; 3 V; DBS; I/Q signals; LSB; QPSK demodulator; auto-zero offset cancellation; comparators; conversion rate; differential nonlinearity error; digital TV; digital domain; direct broadcasting for satellite; double-metal CMOS technology; doublepoly CMOS technology; dual CMOS A/D converter; dual flash architecture; experimental prototype; front-end receiver; integral nonlinearity error; resolution; system performance; Baseband; Clocks; Demodulation; Digital signal processing; Large scale integration; Neodymium; Quadrature phase shift keying; Satellite broadcasting; Signal resolution; TV broadcasting;
Journal_Title :
Consumer Electronics, IEEE Transactions on
