Josephson edge-triggered gates for sequential circuits

A Josephson sequential logic family with a very wide operating margin (+or-67%) and insensitivity to global parameter variations is proposed. Derived from the original idea of the edge-triggered latching comparator by C. Hamilton et al. (see IEEE Trans Magnetics, vol.MAG-21, p.197-9, 1985), this logic gate consists of a pair of conventional gates in series biased by a delay clock. In normal operation, switching occurs in one and only one of the gates, depending on which one has the smaller critical current. The authors have built and tested a few circuits to illustrate this logic gate design: a 32-b shift register designed by OR gates with +or-42% bias margin and +or-89% input margin, a 4-b pseudorandom sequence generator designed by exclusive-OR gates with +or-27% bias margin and +or-78% input margin, and cross section of a 6-b NOR gate decoder with +or-33% bias margin.<>