Title :
A 5.4-Gbit/s Adaptive Continuous-Time Linear Equalizer Using Asynchronous Undersampling Histograms
Author :
Kim, Wang-Soo ; Seong, Chang-Kyung ; Choi, Woo-Young
Author_Institution :
Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea
Abstract :
We demonstrate a new type of adaptive continuous-time linear equalizer (CTLE) based on asynchronous undersampling histograms. Our CTLE automatically selects the optimal equalizing filter coefficient among several predetermined values by searching for the coefficient that produces the largest peak value in histograms obtained with asynchronous undersampling. This scheme is simple and robust and does not require clock synchronization for its operation. A prototype chip realized in 0.13-μm CMOS technology successfully achieves equalization for 5.4-Gbit/s 231 - 1 pseudorandom bit sequence data through 40-, 80-, and 120-cm PCB traces and 3-m DisplayPort cable. In addition, we present the results of statistical analysis with which we verify the reliability of our scheme for various sample sizes. The results of this analysis are confirmed with experimental data.
Keywords :
CMOS integrated circuits; adaptive equalisers; filtering theory; printed circuits; random sequences; reliability; statistical analysis; CMOS technology; CTLE; DisplayPort cable; PCB traces; adaptive continuous-time linear equalizer; asynchronous undersampling histograms; bit rate 5.4 Gbit/s; clock synchronization; optimal equalizing filter coefficient; pseudorandom bit sequence data; reliability; size 0.13 mum; size 120 cm; size 3 m; size 40 cm; size 80 cm; statistical analysis; Adaptive equalizers; CMOS integrated circuits; Clocks; Histograms; Monitoring; Semiconductor device measurement; Adaptive equalization; asynchronous undersampling histogram; continuous-time linear equalizer (CTLE);
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2012.2208671
