A fully programmable systolic pipelined digital video encoder for NTSC/PAL/PALplus compatibility on a 4:3 screen

An encoder is proposed that supports NTSC and PAL systems. In addition, it also permits the PALplus standard mode, that is compatible to a 16:9 wide screen, on a 4:3 screen. In order for this to be realized the vertical and horizontal synchronous timing are fully programmable and the encoder is designed in a systolic pipelined architecture with a double pixel clock to increase the internal processing speed. Also, we have mainly concentrated on reducing the gate counts of the submodules such as the letter-box converter, color converter matrix, low pass filter, interpolator, and color modulator. The encoder can accept RGB and YCbCr as the input pixel signal with a speed of 10-15 Mpps. The outputs are a Y/C (S-video) signal and a composite signal. We have modeled the encoder in Verilog-HDL and verified its overall operation by feeding the top module with a color bar test signal. The encoder, which was implemented by 0.6 μm CMOS technology, contains about 42 k gates