A high performance hardware architecture for multi-frame hierarchical motion estimation

This paper presents the architecture design and FPGA implementation of a multi-frame hierarchical motion estimation (MFHME) circuit. The target application of the circuit is high quality motion-compensated video frame rate up-conversion that requires dense motion fields (MF) and accurate motion trajectories. To obtain accurate motion trajectories, the circuit uses two frames as references and calculates the block matching errors for both the luminance and chrominance components of the images. In addition, the sum of squared pixel differences, instead of the sum of the absolute pixel differences, is used as the metric of the block matching errors in order to further improve the accuracy of the estimated motion trajectories. To achieve low computation complexity, the circuit has been designed based on a hierarchical structure and a pre-computed lookup table is used to provide the squared pixel differences. The implementation result shows that the circuit is able to support the frame rate up-conversion of high definition video (1080P format) from 30 to 60 frames per second at a clock frequency of 55 MHz.