A Leakage-Current-Recycling Phase-Locked Loop in 65 nm CMOS Technology

Author

Lee, I-Ting ; Tsai, Yun-Ta ; Liu, Shen-Iuan

Author_Institution

Grad. Inst. of Electron. Eng. & Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

47

Issue

11

fYear

2012

Firstpage

2693

Lastpage

2700

Abstract

A leakage-current-recycling technique is presented for phase-locked loops (PLLs) in nanoscale CMOS technology. The leakage current of the PMOS capacitor in a PLL is recycled to supply the power for a voltage-controlled oscillator, a divider, and a dual-mode phase-frequency detector. This PLL is fabricated in a 65 nm CMOS technology. The measured peak-to-peak jitter and rms jitter of this PLL at 640 MHz are 52.2 ps and 9.6 ps, respectively. Its power consumption is 1.2 mW for a 1.2 V supply voltage.

Keywords

CMOS analogue integrated circuits; jitter; leakage currents; phase locked loops; voltage dividers; voltage-controlled oscillators; CMOS technology; PLL; PMOS capacitor; dual-mode phase-frequency detector; frequency 640 MHz; leakage-current-recycling phase-locked loop; peak-to-peak jitter measurement; power 1.2 mW; power consumption; rms jitter; size 65 nm; time 52.2 ps; time 9.6 ps; voltage 1.2 V; voltage dividers; voltage-controlled oscillator; Capacitors; Clocks; Leakage current; Phase frequency detector; Phase locked loops; Voltage control; Voltage-controlled oscillators; Leakage current; MOS capacitor; leakage tracking; leakage-current recycling; low power; phase-locked loops;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2012.2209810

Filename

6289390