Title :
A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems
Author :
Koo, Yido ; Huh, Hyungki ; Cho, Yongsik ; Lee, Jeongwoo ; Park, Joonbae ; Lee, Kyeongho ; Jeong, Deog-Kyoon ; Kim, Wonchan
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., South Korea
fDate :
5/1/2002 12:00:00 AM
Abstract :
A fully integrated CMOS frequency synthesizer for PCS- and cellular-CDMA systems is integrated in a 0.35-μm CMOS technology. The proposed charge-averaging charge pump scheme suppresses fractional spurs to the level of noise, and the improved architecture of the dual-path loop filter makes it possible to implement a large time constant on a chip. With current-feedback bias and coarse tuning, a voltage-controlled oscillator (VCO) enables constant power and low gain of the VCO. Power dissipation is 60 mW with a 3.0-V supply. The proposed frequency synthesizer provides 10-kHz channel spacing with phase noise of -121 dBc/Hz in the PCS band and -127 dBc/Hz in the cellular band, both at 1-MHz offset frequency
Keywords :
CMOS integrated circuits; UHF integrated circuits; cellular radio; circuit tuning; code division multiple access; frequency synthesizers; integrated circuit noise; personal communication networks; phase locked loops; phase noise; 0.35 micron; 0.86 to 1.98 GHz; 3 V; 60 mW; CMOS RFIC; CMOS frequency synthesizer; PCS-CDMA systems; PLL; VCO; cellular-CDMA systems; charge-averaging charge pump scheme; coarse tuning; current-feedback bias; dual-path loop filter; fractional spurs suppression; fractional-N-type prescaler; phase-locked loop; voltage-controlled oscillator; 1f noise; CMOS technology; Channel spacing; Charge pumps; Filters; Frequency synthesizers; Noise level; Power dissipation; Tuning; Voltage-controlled oscillators;
Journal_Title :
Solid-State Circuits, IEEE Journal of
