Bitline GND sensing technique for low-voltage operation FeRAM

Author

Kawashima, Shoichiro ; Endo, Toru ; Yamamoto, Akira ; Nakabayashi, Ken´ichi ; Nakazawa, Mitsuharu ; Morita, Keizo ; Aoki, Masaki

Author_Institution

Fujitsu Labs. Ltd., Tokyo, Japan

Volume

37

Issue

5

fYear

2002

fDate

5/1/2002 12:00:00 AM

Firstpage

592

Lastpage

598

Abstract

In this sensing technique, pMOS charge transfer maintains the bitline level near the GND when the plate line goes high. It gives 0.5-V higher readout voltages across the cell capacitors and enables a 0.4-V higher differential amplitude in a 512-cell per bitline structure compared with the conventional high-impedance bitline sensing technique. Using the shifted bias plate line layout, only eight cells and eight sense amplifiers per cell mat are activated, and simulations show 8.06 mW at 3 V and 5 MHz, which is about the same power consumption as the conventional device

Keywords

cellular arrays; ferroelectric storage; low-power electronics; random-access storage; 3 V; 5 MHz; 8.06 mW; FeRAM; bitline GND sensing technique; bitline level; cell capacitors; differential amplitude; ferroelectric memories; low-voltage operation; pMOS charge transfer; power consumption; readout voltages; sense amplifiers; shifted bias plate line layout; Capacitors; Degradation; Energy consumption; Ferroelectric films; Ferroelectric materials; Hysteresis; Nonvolatile memory; Polarization; Random access memory; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.997852

Filename

997852