A 400-MHz, 12-bit, 18-mW, IF digitizer with mixer inside a sigma-delta modulator loop

Author

Namdar, Ardeshir ; Leung, Bosco H.

Author_Institution

Philsar Semicond. Inc., Nepean, Ont., Canada

Volume

34

Issue

12

fYear

1999

fDate

12/1/1999 12:00:00 AM

Firstpage

1765

Lastpage

1776

Abstract

A 0.8-μ BiCMOS, 400-MHz intermediate-frequency digitizer based on embedding a down-conversion mixer inside a sigma-delta modulator together with a reconstruction filter in the feedback path has been developed. The digitizer, when subsampled with a clock of 20 MHz, achieves a measured resolution of 12 bits for a 40-kHz bandwidth and dissipates 18 mW of power. The third harmonic distortion (HD₃) is less than -90 dBc for a -4-dB input, and the third-order intermodulation product (IM₃) is less than -70 dBc for a -8-dB input, with a full-scale voltage of 0.5 V. The chip area is 1.5 mm²

Keywords

BiCMOS integrated circuits; circuit feedback; harmonic distortion; intermodulation; mobile radio; sigma-delta modulation; 0.5 V; 0.8 micron; 12 bit; 18 mW; 40 kHz; 400 MHz; BiCMOS; IF digitizer; chip area; down-conversion mixer; feedback path; full-scale voltage; reconstruction filter; resolution; sigma-delta modulator loop; third harmonic distortion; third-order intermodulation product; Bandwidth; BiCMOS integrated circuits; Clocks; Delta-sigma modulation; Digital modulation; Distortion measurement; Feedback; Harmonic distortion; Power harmonic filters; Power measurement;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.808901

Filename

808901