DocumentCode
1276530
Title
A 65-mW, 10-bit, 40-Msample/s BiCMOS Nyquist ADC in 0.8 mm2
Author
Hoogzaad, Gian ; Roovers, Raf
Author_Institution
Philips Res. Lab., Eindhoven, Netherlands
Volume
34
Issue
12
fYear
1999
fDate
12/1/1999 12:00:00 AM
Firstpage
1796
Lastpage
1802
Abstract
This paper describes the design of a 10-bit, 40-MSample/s analog-to-digital converter (ADC) based on a cascaded folding and interpolating architecture. The folding and interpolating factors are optimized for low power. The ADC features balanced circuit design, a newly developed shifted averaging technique, and stacked circuits for analog and digital folding. The untrimmed ADC dissipates 65 mW from a single 5-V supply. The fully differential ADC achieves 9.2 effective bits for a 1.6-Vpp input signal. Its resolution bandwidth is 20 MHz. The ADC is realized in a 7-GHz, 0.6-μm BiCMOS process and measures 0.8 mm2
Keywords
BiCMOS integrated circuits; analogue-digital conversion; cascade networks; low-power electronics; 0.6 micron; 10 bit; 20 MHz; 5 V; 65 mW; 7 GHz; BiCMOS analog-to-digital converter; Nyquist sampling; balanced circuit design; cascaded architecture; differential circuit; folding; interpolation; low power circuit; shifted averaging; stacked circuits; Analog-digital conversion; Bandwidth; BiCMOS integrated circuits; CMOS process; CMOS technology; Circuit synthesis; Dynamic range; Interference; Pipelines; Signal resolution;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.808904
Filename
808904
Link To Document