High-Performance Junctionless MOSFETs for Ultralow-Power Analog/RF Applications

Author

Ghosh, Dipankar ; Parihar, Mukta Singh ; Armstrong, G. Alastair ; Kranti, Abhinav

Author_Institution

Low Power Nanoelectron. Res. Group, Indian Inst. of Technol. (IIT) Indore, Indore, India

Volume

33

Issue

10

fYear

2012

Firstpage

1477

Lastpage

1479

Abstract

In this letter, we demonstrate the usefulness of ultralow-power (ULP) junctionless (JL) MOSFETs in achieving improved analog/RF metrics as compared to nonunderlap and underlap MOSFETs. At a drain current (I_ds) of 10 μA/μm, JL devices achieve two times higher values of cutoff frequency (fT) and maximum oscillation frequency (f_MAX) along with 65% improvement in voltage gain (A_VO) in comparison to conventional nonunderlap MOSFETs. ULP JL devices, which do not require source/drain (S/D) profile optimization, can perform comparably to underlap devices, thereby relaxing the stringent process constraints associated with S/D profile optimization in nanoscale devices. The results highlight new opportunities for realizing future ULP analog/RF design with JL transistors.

Keywords

MOSFET; analogue circuits; low-power electronics; microwave field effect transistors; optimisation; S-D profile optimization; ULP JL MOSFET; ULP JL devices; ULP analog-RF design; high-performance junctionless MOSFET; improved analog-RF metrics; maximum oscillation frequency; nanoscale devices; nonunderlap MOSFET; source-drain profile optimization; stringent process constraints; ultralow-power junctionless MOSFET; ultralowpower analog-RF applications; voltage gain; Capacitance; Cutoff frequency; Logic gates; MOSFETs; Performance evaluation; Radio frequency; Analog/RF; double-gate MOSFET; junctionless (JL) transistor; ultralow power (ULP); underlap source/drain (S/D);

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2012.2210535

Filename

6293845