• DocumentCode
    1278143
  • Title

    Speed superiority of scaled double-gate CMOS

  • Author

    Fossum, Jerry G. ; Ge, Lixin ; Chiang, Meng-Hsueh

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
  • Volume
    49
  • Issue
    5
  • fYear
    2002
  • fDate
    5/1/2002 12:00:00 AM
  • Firstpage
    808
  • Lastpage
    811
  • Abstract
    Unloaded ring-oscillator simulations, performed with a generic process/physics-based compact model for double-gate (DG) MOSFETs and supplemented with model-predicted on-state currents and gate capacitances for varying supply voltages (VDD), are used to show and explain the speed superiority of extremely scaled DG CMOS over the single-gate (e.g., bulk-Si) counterpart. The DG superiority for unloaded circuits is most substantive for low VDD < ~1 V
  • Keywords
    CMOS integrated circuits; MOSFET; circuit simulation; delays; high-speed integrated circuits; integrated circuit modelling; semiconductor device models; 1 V; CMOS modeling; double-gate MOSFETs; gate capacitances; model-predicted on-state currents; process/physics-based compact model; propagation delay; scaled double-gate CMOS; speed superiority; unloaded ring-oscillator simulations; Analytical models; CMOS process; Circuits; Inverters; MOSFETs; Medical simulation; Parasitic capacitance; Predictive models; Semiconductor device modeling; Voltage;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/16.998588
  • Filename
    998588
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1278143