Title :
The effect of high-K gate dielectrics on deep submicrometer CMOS device and circuit performance
Author :
Mohapatra, Nihar R. ; Desai, Madhav P. ; Narendra, Siva G. ; Rao, V. Ramgopal
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol., Bombay, India
fDate :
5/1/2002 12:00:00 AM
Abstract :
The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities (Kgate) using two-dimensional (2-D) device and Monte Carlo simulations. The gate-to-channel capacitance and parasitic fringe capacitances are extracted using a highly accurate three-dimensional (3-D) capacitance extractor. It is observed that there is a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance in addition to an increase in internal fringe capacitance, when the conventional silicon dioxide is replaced by a high-K gate dielectric. The lower parasitic outer fringe capacitance is beneficial for the circuit performance, while the increase in internal fringe capacitance and the decrease in the gate-to-channel capacitance will degrade the short channel performance contributing to higher DIBL, drain leakage, and lower noise margin. It is shown that using low-K gate sidewalls with high-K gate insulators can decrease the fringing-induced barrier lowering. Also, from the circuit point of view, for the 70-nm technology generation, the presence of an optimum Kgate for different target subthreshold leakage currents has been identified
Keywords :
CMOS integrated circuits; MOSFET; Monte Carlo methods; capacitance; circuit simulation; dielectric thin films; integrated circuit modelling; integrated circuit noise; leakage currents; permittivity; semiconductor device models; 70 nm; 70-nm technology generation; CMOS inverter; DIBL; Monte Carlo simulations; circuit simulation; deep submicrometer CMOS circuit performance; deep submicrometer CMOS devices; dielectric permittivity range; drain leakage; fringing-induced barrier lowering; gate-to-channel capacitance; high permittivity gate dielectrics; high-K gate dielectrics; high-K gate insulators; low-K gate sidewalls; noise margin; parasitic fringe capacitances; short channel performance; target subthreshold leakage currents; three-dimensional capacitance extractor; two-dimensional device simulations; Acoustical engineering; Circuit noise; Circuit optimization; Degradation; Dielectric devices; High K dielectric materials; Parasitic capacitance; Permittivity; Silicon compounds; Two dimensional displays;
Journal_Title :
Electron Devices, IEEE Transactions on
