Asynchronous design for programmable digital signal processors

Author

Meng, Teresa H Y ; Brodersen, Robert W. ; Messerschmitt, David G.

Author_Institution

Dept. of Electr. Eng., Stanford Univ., CA, USA

Volume

39

Issue

4

fYear

1991

fDate

4/1/1991 12:00:00 AM

Firstpage

939

Lastpage

952

Abstract

A systematic procedure for designing fully asynchronous programmable processors from an architectural description is described. Design issues such as pipelining, interconnection circuit specifications, data flow control, program flow control, feedback and initialization, I/O (input/output) interface, and processor architecture are discussed. The system-level tradeoffs of using synchronous design versus asynchronous design are addressed. Simulation results of an asynchronous version of a commercial digital signal processor are given

Keywords

circuit CAD; digital signal processing chips; logic CAD; parallel architectures; pipeline processing; CAD; asynchronous design; data flow control; feedback; initialization; input/output interface; interconnection circuit specifications; pipelining; processor architecture; program flow control; programmable digital signal processors; CMOS logic circuits; Circuit simulation; Circuit synthesis; Clocks; Computer architecture; Digital signal processors; Signal design; Signal processing; Synchronization; Timing;

fLanguage

English

Journal_Title

Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1053-587X

Type

jour

DOI

10.1109/78.80917

Filename

80917